In the field of mobile communication using mobile phones or the like, it is becoming general to handle high frequency signals of several hundreds of megahertz, and this raises needs for semiconductor devices excellent in high-frequency characteristics. For example, semiconductor devices such as CMOS-IC and high-voltage-resistant-type IC adopt a so-called SOI wafer which is configured by forming a silicon oxide insulating layer (buried oxide film) on a silicon single crystal substrate (also referred to as “base wafer”, hereinafter), and by stacking thereon another silicon single crystal layer as an SOI (silicon on insulator) layer. For the case where the SOI wafer is applied to semiconductor devices for high-frequency use, it is necessary to use a silicon single crystal having a large resistivity as the base wafer, in view of suppressing high-frequency loss.
Bonding process is known as a representative method of fabricating the SOI wafer. In the bonding process, a first silicon single crystal substrate as a base wafer and a second silicon single crystal substrate later made into an SOI layer which serves as a device formation area (also referred to as “bond wafer”, hereinafter) are bonded while placing a silicon oxide film in between, and the bond wafer is then thinned to a desired thickness to thereby convert the bond wafer into the SOI layer.
Of several methods of thinning the bond wafer, Smart-Cut process (registered trademark) is known as a simple method making it possible to obtain a uniform thickness in a relatively easy manner. The process is characterized in that hydrogen ion is implanted from the bonding surface (referred to as first main surface) of the bond wafer so as to form therein a heavily hydrogen doped layer at a predetermined depth, and after the bonding, the bond wafer is separated at the position of the heavily hydrogen doped layer.
The above-described method, however, suffers from the drawbacks described in the next. That is, as shown in FIG. 8A, in the Smart-Cut process, an SOI wafer 50′ (reference numeral 7 denotes a base wafer, and reference numeral 2 denotes a silicon oxide film) obtained after the separation will have, on the surface of the SOI layer 8, a damaged layer 8a caused by the ion implantation, and will have a surface roughness of the separation surface per se considerably larger than that of a mirror surface of a Si wafer of a general product level. In order to remove the damaged layer 8a, the conventional process has adopted mirror polishing (generally referred to as touch polishing, carried out by mechano-chemical polishing) with a small polishing stock removal so as to obtain a mirror surface. This method may be successful in removing roughness component with a short wavelength on the separation surface in a relatively easy manner, but is disadvantageous in that another intra-wafer non-uniformity in the polishing stock removal is newly added. The obtained SOI layer will consequently have distribution of thickness t of 1 to 2 nm as expressed by standard deviation σ1 within a single wafer, as shown in FIG. 8B. It is also to be noted that, as shown in FIG. 8C, the distribution amounts approximately 3 nm or more as expressed by standard deviation σ2 of the thickness t (t1, t2, t3) among wafers in a wafer lot having the same specification. In particular for the case where the surface roughness of the separation surface is large, the thickness distribution of the polished SOI layer becomes more likely to worsen because the polishing stock removal becomes larger.
In general, the depth of formation of the heavily hydrogen doped layer is increased when a thick SOI layer is required, and the depth of formation of the heavily hydrogen doped layer is reduced when a thin SOI layer is required. On the other hand, it has generally been believed that hydrogen must be implanted to a predetermined critical dose or above irrespective of the depth of formation of the heavily hydrogen doped layer, in order to cause the separation, and therefore even for the case where an extremely thin SOI layer is to be formed, an ion dose level equivalent to that used for formation of a relatively thick SOI layer has been adopted. Roughness of the separation surface will therefore inevitably becomes large, also for formation of a thin SOI layer, to a comparable degree with that for the case where a thick SOI layer is formed, so that influence of intra-wafer non-uniformity in the polishing stock removal will relatively be enlarged as the thickness of the SOI layer decreases.
This sort of non-uniformity in the thickness is inevitable in the light of current technical level of mirror polishing, and may not specifically raise a serious problem so far as the thickness of the SOI layer remains at a level of approximately 100 nm or more. However in recent accelerating trends in further micronization and higher integration of CMOS-LSI, which is a major application field of the SOI wafer, a film of 100 nm thick or around which has been recognized as a ultra-thin film up to several years before is now no more a matter of special surprise. Average thickness required for current ultra-thin SOI layer largely falls below 100 nm, and reaches several tens of nanometer (20 to 50 nm, for example), and in some cases even reaches 10 nm or around. In this case, the above-described level of non-uniformity in the thickness reaches ten to several tens of percent of a target average thickness, so that it is apparent that the non-uniformity directly results in quality variation of the semiconductor devices using the SOI wafer, and in lowered production yield.
It is therefore an object of the present invention to provide a method of fabricating an SOI wafer capable of suppressing both of variations in the intra-wafer and inter-wafer uniformity in the thickness of the SOI layer to a sufficiently low level, even for the case where a required level of the thickness of the SOI layer is extremely small, and of suppressing the quality variation and improving production yield even for the case where the SOI wafer is processed into super-micronized or highly integrated CMOS-LSI and so forth.